DDR3 SDRAM

In computing, DDR3 SDRAM or double-data-rate three synchronous dynamic random access memory is a random access memory interface technology used for high bandwidth storage of the working data of a computer or other digital electronic devices. DDR3 is part of the SDRAM family of technologies and is one of the many DRAM (dynamic random access memory) implementations.

DDR3 SDRAM is an improvement over its predecessor, DDR2 SDRAM, and the two are not compatible. The primary benefit of DDR3 is the ability to transfer at twice the data rate of DDR2 (I/O at 8× the data rate of the memory cells it contains), thus enabling higher bus rates and higher peak rates than earlier memory technologies. In addition, the DDR3 standard allows for chip capacities of 512 megabits to 8 gigabits, effectively enabling a maximum memory module size of 16 gigabytes.

With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

DDR3 is a DRAM interface specification; the actual DRAM arrays that store the data are the same as in any other type of DRAM, and have similar performance.

Contents 1 Overview 1.1 Latencies 2 Extensions 3 Modules 3.1 JEDEC standard modules 4 Feature summary 5 Market penetration 6 Successor 7 See also 8 References

Overview

DDR3 memory provides a reduction in power consumption of 30% compared to DDR2 modules due to DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5 V. The 1.5 V supply voltage works well with the 90 nanometer fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors to reduce leakage of current.^[1]

According to JEDEC^[2] the maximum recommended voltage is 1.575 volts and should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level.

The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8-burst-deep prefetch buffer, in contrast to DDR2's 4-burst-deep or DDR's 2-burst-deep prefetch buffer.

DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on the rising clock edge, and the other, on the falling. In comparison, DDR2's current range of data transfer rates is 400–1066 MT/s using a 200–533 MHz I/O clock, and DDR's range is 200–400 MT/s based on a 100–200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffers is required.

DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007^[3] based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800).^[4] The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD's first socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3.

DDR3 DIMMs have 240 pins, are electrically incompatible with DDR2 and have a different key notch location.^[5] DDR3 SO-DIMMs have 204 pins.^[6]

GDDR3 memory, having a similar name but being from an entirely dissimilar technology, has been in use for graphic cards. GDDR3 has sometimes been incorrectly referred to as "DDR3".

Latencies

While the typical latencies for a JEDEC DDR2 device were 5-5-5-15, the standard latencies for the JEDEC DDR3 devices are 7-7-7-20 for DDR3-1066 and 7-7-7-24 for DDR3-1333.

DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.

As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release.^[7] CAS latency of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns.

Example:

(CAS ÷ DATA RATE) × 2000 = X ns

(7 ÷ 1333) × 2000 = 10.5026 ns

Extensions

Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to enable enthusiast performance extensions to the traditional JEDEC SPD specifications for DDR3 SDRAM.^[8]

Modules

JEDEC standard modules

Standard name	Memory clock (MHz)	Cycle time (ns)	I/O bus clock (MHz)	Data rate (MT/s)	Module name	Peak transfer rate (MB/s)	Timings (CL-nRCD-nRP)
DDR3-800D DDR3-800E	100	10	400	800	PC3-6400	6400	5-5-5 6-6-6
DDR3-1066E DDR3-1066F DDR3-1066G	133	71/2	533	1066	PC3-8500	8533	6-6-6 7-7-7 8-8-8
DDR3-1333F* DDR3-1333G DDR3-1333H DDR3-1333J*	166	6	667	1333	PC3-10600	10667	7-7-7 8-8-8 9-9-9 10-10-10
DDR3-1600G* DDR3-1600H DDR3-1600J DDR3-1600K	200	5	800	1600	PC3-12800	12800	8-8-8 9-9-9 10-10-10 11-11-11
DDR3-1866J* DDR3-1866K DDR3-1866L DDR3-1866M*	233	42/7	933	1866	PC3-14900	14933	10-10-10 11-11-11 12-12-12 13-13-13
DDR3-2133K* DDR3-2133L DDR3-2133M DDR3-2133N*	266	33/4	1066	2133	PC3-17000	17066	11-11-11 12-12-12 13-13-13 14-14-14

* optional

Note: All above listed are specified by JEDEC as JESD79-3D.^[9] All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest purported speed reached was equivalent to DDR3-2544 as of May 2010.^[10]

DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

In addition to bandwidth and capacity variants, modules can

1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E. ^[11]
2. Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, PC3-6400R ECC is the same module but with additional ECC.
3. Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.

Feature summary

DDR3 SDRAM components

• Introduction of asynchronous RESET pin
• Support of system-level flight-time compensation
• On-DIMM mirror-friendly DRAM pinout
• Introduction of CWL (CAS write latency) per clock bin
• On-die I/O calibration engine
• READ and WRITE calibration

DDR3 modules

• Fly-by command/address/control bus with on-DIMM termination
• High-precision calibration resistors
• Are not backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard^[12]

Technological advantages compared to DDR2

• Higher bandwidth performance, up to 2133 MT/s standardized
• Slightly improved latencies as measured in nanoseconds
• Higher performance at low power (longer battery life in laptops)
• Enhanced low-power features

Market penetration

Although DDR3 was launched in 2007, DDR3 sales are not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008^[13] (the same view had been stated by market intelligence company DRAMeXchange over a year earlier in April 2007.^[14]) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II processors from AMD, both of which have internal memory controllers: the latter recommends DDR3, the former requires it. IDC stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAM units sold in 2009, rising to 72% by 2011.^[15]

Successor

It was revealed at the Intel Developer Forum in San Francisco 2008 that the successor to DDR3 will be known as DDR4. It is currently in the design stage, and is expected to be released in 2012.^[16] When released, it is expected to run at 1.2 volts or less,^[17][18] versus the 1.5 volts of DDR3 chips and have in excess of 2 billion data transfers per second.

See also

• Dual-channel architecture
• Triple-channel architecture
• List of device bandwidths

References

Types of DRAM Asynchronous FPM RAM · EDO RAM Synchronous SDRAM · DDR SDRAM · Mobile DDR · DDR2 SDRAM · DDR3 SDRAM · DDR4 SDRAM Graphics VRAM · DDR2 · GDDR3 · GDDR4 · DDR3 · GDDR5 Rambus RDRAM · XDR DRAM · XDR2 DRAM